This application claims the benefit of priority under 35 U.S.C. xc2xa7119(a) of Korean Patent Application No. 2001-75868, filed on Dec. 3, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to an apparatus for testing semiconductor integrated circuits and, more particularly, to an apparatus for simultaneously testing a plurality of semiconductor integrated circuits.
Generally, a process for fabricating semiconductor integrated circuits comprises steps for testing whether the semiconductor integrated circuit operates properly, and for detecting which portions are not operating correctly.
Test apparatuses for testing steps can typically be categorized as either single test apparatuses or parallel test apparatuses. The single test apparatuses can test only one semiconductor integrated circuit at a time, while the parallel test apparatuses can test a plurality of semiconductor integrated circuits at the same time. Therefore, the parallel test apparatuses can be very useful for production of integrated circuits on a large scale. Such parallel test apparatuses are found in Korean Patent Publication No. 1999-62211 entitled xe2x80x9cTEST SYSTEM FOR SEMICONDUCTOR DEVICE,xe2x80x9d and Korean Patent Publication No. 2000-17238 entitled xe2x80x9cTEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME.xe2x80x9d
FIG. 1 illustrates an example of a parallel test apparatus.
Referring to FIG. 1, the test apparatus 1 comprises memory sets MS0-MSn that correspond to Integrated circuits DUT0_DUTn being tested, and store test data T_DATA0-T_DATAn for testing the corresponding integrated circuits DUT0_DUTn. A driving circuit 30 transfers the test data T_DATA0-T_DATAn output from the memory sets MS0-MSn to input terminals IN0-1N3 of each of the integrated circuits DUT0-DUTn. A timing controller 50 controls the driving circuit 30. Also, the test apparatus 1 comprises a wave generator 60, an analog unit 70, and comparators C0-Cn. The wave generator 60 and analog unit 70 are described in detail below. The comparators C0-Cn correspond to the integrated circuits DUT0-DUTh. The comparators C0-Cn compare signals, which are output from output terminals OUT0-OUT3 of the integrated circuits DUT0_DUTn, with pre-set expected values (expected data), and generate comparison result signals. A controller 10 controls components of the test apparatus 1. In the test apparatus 1 illustrated in FIG. 1, the tested integrated circuits DUT0-DUTn each has four input terminals IN0-IN3 as well as four output terminals OUT0-OUT3.
Each of the memory sets MS0-MSn includes four memory units M0-M3, which correspond to the input terminals IN0-IN3 included in each of the corresponding integrated circuits DUT0-DUTn. Each of the memories M0-M3 stores the test data T_DATA0-T_DATAn, which will be input to the input terminals IN0-IN3 of the corresponding integrated circuit.
The driving circuit 30 includes sub driving circuits SD0-SDn that correspond to the integrated circuits DUT0-DUTn. Each of the sub driving circuits SD0-SDn includes drivers D0-D3 that correspond to the input terminals IN0-IN3 of the corresponding integrated circuit.
The foregoing conventional test apparatus 1 operates as follows. The test data T_DATA0-T_DATAn, which are stored in the memories M0-M3 of each of the memory sets MS0-MSn, are output from the respective memories M0-M3 in response to a control signal of the controller 10.
The test data T_DATA0-T_DATAn are transferred from the memory sets MS0-MSn to the sub-driving circuits SD0-SDn, respectively. Namely, the test data T-DATA0 Is transferred from the memory set MS0 to the sub-driving circuit SD0; the test data T-DATA1 is transferred from the memory set MS1 to the sub driving circuit SD1; and the test data T-DATAn Is transferred from the memory set MSn to the sub driving circuit SDn. In response to control signals of the timing controller 50, the wave generator 60, and the analog unit 70, the sub driving circuits SD0-SDn transfer the test data T_ATA0-T_DATAn, which are input from the memory sets MS0-MSn, to the Input terminals IN0-IN3 of the integrated circuits DUT0-DUTn being tested.
The timing controller 50 controls the timings of signals output from the drivers D0-D3 in the sub-driving circuits SD0-SDn. The wave generator 60 sets the waveforms of signals output from the drivers D0-D3 in the sub-driving circuits SD0-SDn. The analog unit 70 sets the voltage levels of signals output from the drivers D0-D3, which are included in the sub-driving circuits SD0-SDn, respectively, and also sets expected values for the comparators C0-Cn.
Each of the integrated circuits under test DUT0-DUTn receives the test data T_DATA0-T_DATAn output from the corresponding sub driving circuits SD0-SDn, and generates output signals at the output terminals OUT0-OUT3 in response to the received test data T_DATA0-T_DATAn.
Each of the comparators C1-Cn compares signals, which are generated at the output terminals OUT0-OUT3 of the corresponding integrated circuits DUT0-DUTn, with the expected values, and generates comparison result signals. For example, when the output signals, which are generated at the output terminals OUT0-OUT3 of the integrated circuits DUT0-DUTn, are equal to the reference values (i.e., the corresponding integrated circuits DUT0-DUTn are operating properly), the comparison result signals are low-level. By comparison, when the output signals, which are generated at the output terminals OUT0-OUT3 of the integrated circuits DUT0-DUTn, are not equal to reference values (i.e., the corresponding integrated circuits DUT0-DUTn are not operating properly), the comparison result signals are high-level.
Generally, integrated circuits, which are simultaneously tested in the test apparatus 1, have the same circuit configuration and the same input/output terminals. Therefore, the same test data T_DATA0-T_DATAn may be used to test whether each of the integrated circuits is operating properly. However, the conventional test apparatus 1 illustrated in FIG. 1 has a separate memory set MS0, MS1, . . . , MSn for each of the integrated circuits DUT0-DUTn being tested. Such a test apparatus 1 needs the same number of memory sets as integrated circuits being tested. The additional memory sets cause an increase in size of the test apparatus 1, and may increase fabrication costs of the test apparatus 1 . Furthermore, as the number of memory sets increases, the controller 10 requires an increased controlling time to read data stored in the memories M0-M3 of the memory sets MS0-MSn, i.e., the pattern loading time increases.
The present invention is directed to a test apparatus, which simultaneously tests multiple semiconductor integrated circuits by applying stored test data to each integrated circuit. The test apparatus includes a set of memory units, each of which stores data used for testing a particular input terminal of each integrated circuit. The test apparatus generates test data for each of the integrated circuits by reproducing the data stored in each of the memory units. Accordingly, the test apparatus need only include a number of memory units equal to the number of input terminals to be tested for each integrated circuit. For example, if four input terminals are being tested for each integrated circuit, only four memory units are required.
The test apparatus includes a sub-test data generator for reproducing the test data stored in the set of memory units in order to generate a reproduced test data set (i.e., sub-test data) for each integrated circuit being tested. Specifically, the sub-test data generator includes one data reproduction unit for each integrated circuit. Each data reproduction unit includes a set of buffers, each of which is connected to a memory unit. The test data stored in each memory unit is transferred to the corresponding buffer in each of the data reproduction units. Each buffer, in turn, transfers the data to a connected driver, which converts the data into an input signal having adequate voltage levels for the integrated circuits. The input signal is then transferred from each driver to a connected input terminal of one of the integrated circuits.
According to the present invention, only one set of memory units to store the test data required for simultaneously testing a plurality of semiconductor integrated circuits. Therefore, the test apparatus of the present invention can be manufactured at a reduced cost compared with a conventional test apparatus, which includes one set of memory units for each integrated circuit being tested.